Design Rule Check (DRC) is a guide to avoid reflections, couplings; signals shape changes etc for Signal Integrity (SI) and also correlated areas, ensuring proper operation of the circuits. This article addresses the performances of straight, right angle, edge and slot configurations on microstrip technology using computer electromagnetic simulation. Phase shift, signal shape distortion in time domain and eye diagram effects on those geometries are verified with 3D field simulations on CST MWS. The goal is to study some canonical cases, which can become much more complex on boards with many layers, circuits and components.